View CY23S08ZXC-1H_4193653.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY23S08
3.3V Zero Delay Buffer
Features

Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations, see Table 3 on page 3 Multiple low-skew outputs 45 ps typical output-output skew(-1) Two banks of four outputs, three-stateable by two select inputs 10 MHz to 133 MHz operating range 65 ps typical cycle-cycle jitter (-1, -1H) Advanced 0.65 CMOS technology Space saving 16-pin 150-mil SOIC/TSSOP packages 3.3V operation Spread AwareTM
The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Table 2 on page 3. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The CY23S08 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 50 A of current draw. The PLL shuts down in two additional cases as shown in Table 2 on page 3. Multiple CY23S08 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY23S08 is available in five different configurations, as shown in Table 3 on page 3. The CY23S08-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The CY23S08-1H is the high-drive version of the -1, and rise and fall times on this device are much faster. The CY23S08-2 enables the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The CY23S08-2H is the high-drive version of the -2, and rise and fall times on this device are much faster. The CY23S08-3 enables the user to obtain 4X and 2X frequencies on the outputs. The CY23S08-4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications.

Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 250 ps.
Logic Block Diagram
/2
REF
PLL
MUX
FBK CLKA1 CLKA2 CLKA3
Extra Divider (-3, -4)
S2 S1
CLKA4
Select Input Decoding
/2
CLKB1 CLKB2 CLKB3
Extra Divider (-2, -2H, -3)
CLKB4
Cypress Semiconductor Corporation Document #: 38-07265 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 05, 2007
[+] Feedback
CY23S08
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC Package Top View
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8 16 15 14
SOIC
13 12 11 10 9
FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
Table 1. Pin Definition - 16 Pin SOIC Package Pin Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[2] CLKA1[3] CLKA2[3] VDD GND CLKB1[3] CLKB2[3] S2[4] S1[4] CLKB3[3] CLKB4[3] GND VDD CLKA3[3] CLKA4[3] FBK Clock output, Bank A Clock output, Bank A 3.3V supply Ground Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input
Description
Input reference frequency, 5V tolerant input
Notes 1. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the CY23S08-2. 2. Weak pull down. 3. Weak pull down on all outputs. 4. Weak pull ups on these inputs.
Document #: 38-07265 Rev. *G
Page 2 of 10
[+] Feedback
CY23S08
Table 2. Select Input Decoding S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three-State Driven Driven Driven CLOCK B1-B4 Three-State Three-State Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N
Table 3. Available CY23S08 Configurations Device CY23S08-1 CY23S08-1H CY23S08-2 CY23S08-2H CY23S08-2 CY23S08-2H CY23S08-3 CY23S08-3 CY23S08-4 Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank A Bank B Bank B Bank A Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference Reference 2 X Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Bank B Frequency Reference Reference Reference/2 Reference/2 Reference Reference Reference or Reference[1] 2 X Reference 2 X Reference
Spread Aware
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see Cypress's application note EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.
Document #: 38-07265 Rev. *G
Page 3 of 10
[+] Feedback
CY23S08
Maximum Ratings
Supply Voltage to Ground Potential................-0.5V to +7.0V DC Input Voltage (Except Ref) .............. -0.5V to VDD + 0.5V DC Input Voltage REF ........................................... -0.5 to 7V Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec.) ....................... 260C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions for CY23S08SC-XX Commercial Temperature Devices
Parameter[5] VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance[6] Description Min 3.0 0 -- -- -- Max 3.6 70 30 15 7 Unit V C pF pF pF
Electrical Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[7] Output HIGH Voltage[7] VIN = 0V VIN = VDD IOL = 8 mA (-1, -2, -3, -4) IOL = 12 mA (-1H, -2H) IOH = -8 mA (-1, -2, -3, -4) IOH = -12 mA (-1H, -2H) Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (-1,-2,-3,-4) Unloaded outputs, 33-MHz REF (-1,-2,-3,-4) Test Conditions Min -- 2.0 -- -- -- 2.4 -- -- -- -- -- Max 0.8 -- 50.0 100.0 0.4 -- 12.0 45.0 70.0 (-1H, -2H) 32.0 18.0 Unit V V A A V V A mA mA mA mA
Power down Supply Current REF = 0 MHz Supply Current
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter[8] t1 t1 t1 t1 t1 Name Output Frequency Output Frequency Output Frequency Output Frequency Output Frequency Duty = t2 / t1 (-1,-2,-3,-4,-1H, -2H) Cycle[7] Duty Cycle[7] = t2 / t1 (-1,-2,-3,-4,-1H, -2H) Test Conditions 30-pF load, -1, -1H, -2, -3 devices 30-pF load, -4 devices 20-pF load, -1H device 15-pF load, -1, -2, -3, devices 15-pF load, -4 devices Measured at VDD/2, FOUT = 66.66 MHz 30-pF load Measured at VDD/2, FOUT <66.66 MHz 15-pF load Min 10 15 10 10 15 40.0 45.0 Typ. -- -- -- -- -- 50.0 50.0 Max 100 100 133.3 140.0 140.0 60.0 55.0 Unit MHz MHz MHz MHz MHz % %
Notes 5. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 6. Applies to both Ref Clock and FBK. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. All parameters are specified with loaded outputs.
Document #: 38-07265 Rev. *G
Page 4 of 10
[+] Feedback
CY23S08
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)
Parameter[8] t3 t3 t3 t4 t4 t4 t5 Name Rise Time[7] Test Conditions Min -- -- -- -- -- -- Typ. -- -- -- -- -- -- 45 -- 105 Max 2.20 1.50 1.50 2.20 1.50 1.25 200 150 Unit ns ns ns ns ns ns ps ps (-1, -2, -3, -4) Measured between 0.8V and 2.0V, 30-pF load
Rise Time[7] (-1, -2, -3, -4) Measured between 0.8V and 2.0V, 15-pF load Rise Time[7] (-1H, -2H) Measured between 0.8V and 2.0V, 30-pF load
Fall Time[7] (-1, -2, -3, -4) Measured between 0.8V and 2.0V, 30-pF load Fall Time[7] (-1, -2, -3, -4) Measured between 0.8V and 2.0V, 15-pF load Fall Time[7] (-1H, 2H) Output to Output Skew on same Bank (-1)[7] Output to Output Skew on same Bank (-1H,-2,-2H,-3)[7] Output to Output Skew on same Bank (-4)[7] Output to Output Skew (-1H, -2H) Output Bank A to Output Bank B Skew (-1,-2, -3) Output Bank A to Output Bank B Skew (-4) Output Bank A to Output Bank B Skew (-1H) Measured between 0.8V and 2.0V, 30-pF load All outputs equally loaded All outputs equally loaded
All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded
-- -- -- -- -- -250 -- 1 -- -- -- -- --
70 -- -- -- -- -- -- -- 65 85 -- -- --
100 200 300 215 250 +275 700
ps ps ps ps ps ps ps V/ns
t6 t7 t8 tJ
Delay, REF Rising Edge to Measured at VDD/2 FBK Rising Edge[7] Device to Device Skew[7] Output Slew Rate[7] Cycle to Cycle Jitter[7] (-1, -1H) Cycle to Cycle Jitter[7] (-2) Cycle to Cycle Jitter[7] (-2) Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on -1H, -2H device using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15, 30-pF loads: 133 MHz, 15-pF load Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 66.67 MHz, loaded outputs 15, 30-pF loads Stable power supply, valid clocks presented on REF and FBK pins
125 300 400 200 1.0
ps ps ps ps ms
tJ tLOCK
Cycle to Cycle Jitter[7] (-3,-4) PLL Lock Time[7]
Document #: 38-07265 Rev. *G
Page 5 of 10
[+] Feedback
CY23S08
Switching Waveforms
Figure 2. Duty Cycle Timing
t1 t2 1.4V 1.4V 1.4V
Figure 3. All Outputs Rise/Fall Time
2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V
OUTPUT
Figure 4. Output-Output Skew
1.4V
OUTPUT
OUTPUT t5
1.4V
Figure 5. Input-Output Propagation Delay
VDD/2
INPUT
FBK t6
VDD/2
Figure 6. Device-Device Skew
VDD/2
FBK, Device 1
FBK, Device 2 t7
VDD/2
Document #: 38-07265 Rev. *G
Page 6 of 10
[+] Feedback
CY23S08
Test Circuits
Figure 7. Test Circuit #1
VDD 0.1 F OUTPUTS V DD 0.1 F GND GND CLK OUT C LOAD
Test Circuit for all parameters except t8
Figure 8. Test Circuit #2 Test Circuit # 2 V DD 0.1 F OUTPUTS 1 K V DD 0.1 F GND GND 1 K CLK out 10 pF
Test Circuit for t8, Output slew rate on -1H device
Document #: 38-07265 Rev. *G
Page 7 of 10
[+] Feedback
CY23S08
Ordering Information
Ordering Code CY23S08SC-1 CY23S08SC-1T CY23S08SI-1 CY23S08SI-1T CY23S08SC-1H CY23S08SC-1HT CY23S08SI-1H CY23S08SI-1HT CY23S08ZC-1H CY23S08ZC-1HT CY23S08SC-2 CY23S08SC-2T CY23S08SI-2 CY23S08SI-2T CY23S08SC-2H CY23S08SC-2HT CY23S08SC-3 CY23S08SC-3T CY23S08SC-4 CY23S08SC-4T CY23S08SI-4 CY23S08SI-4T Pb-free CY23S08SXC-1 CY23S08SXC-1T CY23S08SXI-1H CY23S08SXI-1HT CY23S08ZXC-1H CY23S08SXC-2 CY23S08SXC-2T CY23S08SXC-2H CY23S08SXC-2HT CY23S08SXI-2 CY23S08SXI-2T CY23S08SXC-4 CY23S08SXC-4T CY23S08SXI-4 CY23S08SXI-4T 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Active Active Active Active Active Active Active Active Active Active Active Active Active Active Active Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Not for new design Not for new design Not for new design Obsolete Not for new design Not for new design Not for new design Not for new design Obsolete Active Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Status
Document #: 38-07265 Rev. *G
Page 8 of 10
[+] Feedback
CY23S08
Package Drawings and Dimensions
Figure 9. 16-Lead (150-Mil) SOIC S16
PIN 1 ID
8
1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
Figure 10. 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
PIN 1 ID
1
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
4.90[0.193] 5.10[0.200]
51-85091-*A
Document #: 38-07265 Rev. *G
Page 9 of 10
[+] Feedback
CY23S08
Document History Page
Document Title: CY23S08 3.3V Zero Delay Buffer Document Number: 38-07265 REV. ** *A *B *C *D *E ECN NO. 110530 122863 130951 204201 231100 378878 Issue Date 12/02/01 12/20/02 11/26/03 See ECN See ECN See ECN Orig. of Change SZV RBI RGL RGL RGL RGL Description of Change Change from Spec number: 38-01107 to 38-07265 Added power up requirements to operating conditions information. Corrected the Switching Characteristics parameters to reflect the W152 device and new characterization. Corrected the Block Diagram Fixed Typo in table 2. Added Industrial Temp and Pb Free Devices Added typical char data Removed "Preliminary" Changed output-to-output skew typical value from 90ps to 45ps Added cycle-to-cycle jitter (-2) typical value of 85ps
*F *G
391564 1442823
See ECN See ECN
RGL
WWZ/AESA Updated ordering info with status update. Added new Pb-free part numbers.
(c) Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07265 Rev. *G
Revised September 05, 2007
Page 10 of 10
Spread Aware is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY23S08ZXC-1H

	To Download CY23S08ZXC-1H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .